1. Field of the Invention
The present invention relates to a semiconductor storage device and, particularly, to a technique that prevents interference between a refresh operation and a data access operation in pseudo-SRAM (Static Random Access Memory) using DRAM (Dynamic Random Access Memory) cells.
2. Description of Related Art
Pseudo-SRAM in which a memory cell array is composed of DRAM cells that require a refresh operation for maintaining data and made to function as SRAM is widely used today for its advantages of low cost, high capacity and so on. However, pseudo-SRAM has a disadvantage of the lower throughput speed than SRAM. Further, in order to prevent interference between the refresh operation and a normal data access operation such as reading and writing, a means of adjusting the sequence of executing the both operations is necessary for pseudo-SRAM. If there is an error in the adjustment, a memory bank on which the data access operation is concentrated is not sufficiently refreshed, for example, which can cause the occurrence of a malfunction such as data loss.
Related arts related to pseudo-SRAM are described hereinbelow. Japanese Unexamined Patent Application Publication No. 2003-7054 discloses a semiconductor storage device including one timer means that measures data maintain limit time of a memory cell, a storage circuit that stores refresh information indicating being refreshed for each memory bank, a refresh address designation means that designates a refresh address in a memory bank, and a refresh control means that controls a refresh operation on each memory bank according to the designated refresh address and also detects an unrefreshed memory bank from refresh information and makes control to refresh the detected memory bank for every data maintain limit time.
Further, Japanese Unexamined Patent Application Publication No. 2006-59489 discloses a semiconductor storage device including a control circuit that makes control so that a refresh operation is performed just before a read/write operation (normal data access operation) and latency is always set to a first fixed value in the first mode, and the refresh operation is performed just after the read/write operation and latency is always set to a second fixed value in the second mode during test.
Furthermore, Japanese Unexamined Patent Application Publication No. 2002-298574 discloses DRAM including an execution instruction means that instructs execution of a refresh, an address designation means that designates a row address of a memory cell to be refreshed, and an execution means that refreshes a memory cell at a row address designated by the address designation means when execution of a refresh is instructed from the execution instruction means.